Hardware supported data race detection
Svetlana Jaksic Trial lecture in connection with recruitment ternure track associate prefessor position in software. Svetlana Jaksic
Hovedinnhold
Abstract
Data races belong to the class of concurrency-related errors that are very hard to detect. Variety of static and dynamic tools and methods for data race detection have been developed. In this talk, we will investigate the use of hardware –based tracing facilities for the purpose of detecting potential data races. Modern processors offer advanced facilities for introspection of control flow.
Information about data such as memory addresses has to either be logged explicitly by the running code through additional trace packets in the hardware trace, or no a different software-based channel. Specification language TeSSLa can be compiled to the special FPGA-a based hardware which enables checking the instruction trace augmented with necessary data in parallel to the running system. We present a data race detector based on the lockset algorithm, written in TeSSLa. We discuss options for minimizing the amount of necessary instrumentation through the help of static analysis. We discuss some of the related approaches for prevention of data races and other concurrency errors.